How do you plan to solve it?
module pwm4_basic( input clk,rst, input [3:0]duty, output reg pwm_out ); reg[3:0]cunt; always@(posedge clk)begin if(rst)begin pwm_out<=0; cunt<=0; end else begin cunt<=cunt+1; if(cunt<duty)begin pwm_out<=1; end else pwm_out<=0; end end endmodule