30. PWM with 4-bit Resolution

How do you plan to solve it?

module pwm4_basic (
    input clk, rst,
    input [3:0] duty,
    output reg pwm_out
);
    reg [3:0] cnt;
    always @(posedge clk) begin
        if (rst) begin
            pwm_out <= 1'b0;
            cnt <= 4'd0;
        end else begin
            cnt <= cnt + 1'b1;
            if (cnt < duty) begin
                pwm_out <= 1'b1;
            end else begin
                pwm_out <= 1'b0;
            end
        end
    end
endmodule