How do you plan to solve it?
/*Write your code here*/ module pwm4_basic( input clk, input rst, input[3:0]duty, output reg pwm_out ); reg[3:0]cnt; always @(posedge clk)begin if(rst)begin cnt=1'b0; pwm_out=0; end else begin pwm_out<=(cnt<duty); cnt<=cnt+1; end end endmodule