How do you plan to solve it?
/*Write your code here*/ module pwm4_basic( input clk,rst, input [3:0] duty, output reg pwm_out ); reg [3:0] cnt; always @(posedge clk)begin pwm_out <= rst ? 1'b0 : (cnt<duty); cnt <= rst ? 1'b0 : cnt +1; end endmodule