/*Write your code here*/
module pwm4_basic(input clk,rst, input [3:0]duty, output reg pwm_out);
reg [3:0]cnt;
always @(posedge clk)
begin
/*
cnt <= rst ? 4'b0 : ((cnt==4'b1111)?4'b0:(cnt+1'b1));
pwm_out <= rst ? 1'b0 : ((cnt<duty)?1'b1:1'b0);
*/
cnt <= rst ? 4'b0 : (cnt+4'b1);
pwm_out <= rst ? 1'b0 : (cnt < duty);
end
endmodule