Question.4
In a standard Verilog simulation, what logic state natively outputs to out?
out
wire [3:0] data; wire out = data[12];
Select Answer
The simulation crashes with a segmentation fault.
The index wraps around using modulo arithmetic to data[0]
data[0]
Evaluating the out-of-bounds bit outputs an unknown x state
x
The compiler extrapolates the sign bit
