Question.5
Which Verilog snippet splits the 8-bit data bus into 4-bit high_nibble and low_nibble as shown below?
data
high_nibble
low_nibble
Select Answer
assign {high_nibble, low_nibble} = {data[0:3], data[4:7]};
assign high_nibble = data[3:0]; assign low_nibble = data[7:4];
assign high_nibble = data[7:4]; assign low_nibble = data[3:0];
assign data = {high_nibble, low_nibble};
