How do you plan to solve it?
/*Write solution code here*/ module selector3 ( input wire [7:0] a,b,c, input wire [1:0] sel, output reg [7:0] y ); always@* begin case(sel) 2'd0:y=a; 2'd1:y=b; 2'd2:y=c; 2'd3:y=8'd0; endcase end endmodule