How do you plan to solve it?
/*Write your code here*/
module mx(
input [3:0] a,b,
output [3:0] max
);
assign max = (a[3]&(~b[3])) |
((a[3]~^b[3]) & (a[2]&(~b[2]))) |
((a[3]~^b[3]) & (a[2]~^b[2]) & (a[1]&(~b[1]))) |
((a[3]~^b[3]) & (a[2]~^b[2]) & (a[1]~^b[1]) & (a[0]&(~b[0])))
? a : b;
endmodule
module mn(
input [3:0] a,b,
output [3:0] min
);
assign min = (a[3]&(~b[3])) |
((a[3]~^b[3]) & (a[2]&(~b[2]))) |
((a[3]~^b[3]) & (a[2]~^b[2]) & (a[1]&(~b[1]))) |
((a[3]~^b[3]) & (a[2]~^b[2]) & (a[1]~^b[1]) & (a[0]&(~b[0])))
? b : a;
endmodule
module maxmin4(
input [3:0] a, b, c, d,
output [3:0] max, min
);
wire [3:0] mx1, mx2, mn1, mn2;
mx m1(a, b, mx1);
mx m2(c, d, mx2);
mx m3(mx1, mx2, max);
mn m4(a, b, mn1);
mn m5(c, d, mn2);
mn m66(mn1, mn2, min);
endmodule