59. Absolute Value

module abs8_func (
    input  signed [7:0] a,
    output       [7:0] abs
);
    function [7:0] abs8;
        input signed [7:0] x;
        begin
            abs8 = (x < 0) ? -x : x;
        end
    endfunction

    assign abs = abs8(a);
endmodule

💡Remember

Verilog functions: one return value, no timing controls, great for pure combinational helpers.
Mark inputs/temps signed when doing signed math.
Two’s complement quirk: |-128| in 8 bits is still 8'h80 (wraps), which is fine for this exercise.