71. Arithmetic Logic Unit

How do you plan to solve it?

/*Write your code here*/
module alu4(
    input [3:0] a,
    input [3:0] b,
    input [2:0] op,
    output  reg [3:0] y,
    output reg cf
);
wire [4:0] add_1 = {1'b0, a} + {1'b0, b};
wire [4:0] sub_1 = {1'b0, a} + {1'b0, ~b} + 5'b00001;
always @(*) begin
case(op)
3'b000: begin
    y = add_1[3:0];
    cf = add_1[4];
end
3'b001: begin
    y = sub_1[3:0];
    cf = ~sub_1[4];
end
3'b010: begin
    y = a & b;
    cf = 0;
end
3'b011: begin
    y = a | b;
    cf = 0;
end
3'b100: begin
    y = a ^ b;
    cf = 0;
end
default: begin 
y = 4'b0000;
cf=0;
end
endcase
end
endmodule