71. Arithmetic Logic Unit

How do you plan to solve it?

module alu4(input[3:0] a,
input [3:0] b,
input [2:0] op,
output [3:0] y,
output cf);
wire [4:0] add_s1, sub_s2;
assign add_s1= {1'b0 ,a} + {1'b0, b};
assign sub_s2 = {1'b0, a} + {1'b0,~b} + 5'b00001;
assign y=
  (op==3'b000)? add_s1[3:0]:
  (op==3'b001) ? sub_s2[3:0]:
  (op==3'b010) ? (a & b):
  (op==3'b011) ? (a | b):
  (op==3'b100) ? (a ^ b):
               4'b0000;

// case2 about the  carry
assign cf =
   (op==3'b000)? add_s1[4]:
   (op==3'b001) ? ~sub_s2[4]:
                1'b0;
endmodule