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71. Arithmetic Logic Unit

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Solving Approach

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Code

module alu4(
    input [3:0] a,b,op,
    output reg [3:0] y,
    output reg cf

);
reg[4:0] sum;
always @(*)begin
    case(op)
        3'b0: begin 
            sum = a+b;
            y = sum[3:0];
            cf = sum[4];

        end

        3'b1: begin
            sum = a+~b+1;
            y = sum[3:0];
            cf = sum[4];
        end
        3'b10: begin y = a & b; cf = 0; end
        3'b11: begin y = a | b ; cf = 0; end
        3'b100: begin y = a ^ b; cf = 0; end
        default: begin y = 4'b0000; cf = 0; end

    endcase

end

endmodule

 

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