71. Arithmetic Logic Unit

module alu4 (
    input [3:0] a,
    input [3:0] b,
    input [2:0] op,
    output reg [3:0] y,
    output reg cf
);
    wire [4:0] add5 = {1'b0, a} + {1'b0, b};
    
    always @* begin
        case (op)
            3'd0 : y = add5[3:0];
            3'd1 : y = a - b;
            3'd2 : y = a & b;
            3'd3 : y = a | b;
            3'd4 : y = a ^ b;
            default : y = 4'd0;
        endcase
        case (op)
            3'd0 : cf = add5[4];
            3'd1 : cf = (a < b) ? 1'b1 : 1'b0;
            default : cf = 1'b0;
        endcase
    end
endmodule