71. Arithmetic Logic Unit

How do you plan to solve it?

module alu4(
    input [3:0] a,b,
    input [2:0] op,
    output reg [3:0] y,
    output reg cf
);
    localparam [2:0]
        ADD = 3'b000,
        SUB = 3'b001,
        AND = 3'b010,
        OR = 3'b011,
        XOR = 3'b100;
    
    wire [4:0]add,sub;
    assign add = {1'b0,a} + {1'b0,b};
    assign sub = {1'b0,a} + {1'b0,(~b)} + 5'b1;

    always @(*)begin
        y = 4'd0;
        cf = 0;
        case (op)
            ADD : begin 
                y = add[3:0];
                cf = add[4];
            end
            SUB : begin
                y = sub[3:0];
                cf = (a<b);
            end
            AND : y = a&b;
            OR : y = a|b;
            XOR : y = a^b;
            default : begin y = 4'd0; cf =1'b0;
            end
        endcase
    end
endmodule