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71. Arithmetic Logic Unit

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Solving Approach

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Code

module alu4(
    input  [3:0] a,
    input  [3:0] b,
    input  [2:0] op,
    output reg [3:0] y,
    output reg       cf
);

    reg [4:0] sum;

    always @(*) begin
        y   = 4'b0000;
        cf  = 1'b0;
        sum = 5'b00000;

        case (op)
            3'b000: begin
                sum = {1'b0, a} + {1'b0, b};
                y   = sum[3:0];
                cf  = sum[4];
            end

            3'b001: begin
                sum = {1'b0, a} + {1'b0, ~b} + 5'b00001;
                y   = sum[3:0];
                cf  = ~sum[4];
            end

            3'b010: y = a & b;
            3'b011: y = a | b;
            3'b100: y = a ^ b;

            default: begin
                y  = 4'b0000;
                cf = 1'b0;
            end
        endcase
    end

endmodule

 

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