How do you plan to solve it?
/*Write your code here*/
module alu4(
input [3:0]a,b,
input [2:0]op,
output reg[3:0]y,
output reg cf);
localparam [2:0]
ADD = 3'b000,
SUB = 3'b001,
AND = 3'b010,
OR = 3'b011,
XOR = 3'b100;
wire [4:0] add={1'b0,a}+{1'b0,b};
wire [4:0] sub={1'b0,a}+{1'b0,~b}+5'b1;
always @*
begin
y=4'b0000;
cf=1'b0;
case(op)
ADD : begin
y=add[3:0];
cf=add[4];
end
SUB :begin
y=sub[3:0];
cf=~(sub[4]);
end
AND : y=a&b;
OR : y=a|b;
XOR : y=a^b;
default :
begin y=4'b0000;
cf=1'b0;
end
endcase
end
endmodule