71. Arithmetic Logic Unit

How do you plan to solve it?

/*Write your code here*/
module alu4 (input wire [3:0] a, b,
             input wire [2:0] op,
             output reg [3:0] y,
             output reg cf         );
    reg [4:0] sum, sub;
    always @(*) begin
        case(op)
            3'b000: begin
                sum = a + b;
                cf = sum[4];
                y = sum[3:0];
            end
            3'b001: begin
                sub = a + (~b) + 1;
                cf = sub[4];
                y = sub[3:0];
            end
            3'b010: begin
                y = a & b;
                cf = 0;
            end
            3'b011: begin
                y = a | b;
                cf = 0;
            end
            3'b100: begin
                y = a ^ b;
                cf = 0;
            end
            default: begin
                y = 4'b0000;
                cf = 0;
            end
        endcase
    end
endmodule