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71. Arithmetic Logic Unit

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Code

module alu4(input[3:0]a, input[3:0]b, input[2:0]op, output reg cf, output reg [3:0]y);


    always@(*)begin
        case(op)
            3'b000: {cf,y} = a + b;
            3'b001: {cf, y} = (a + ~b + 1'd1);
            3'b010: {cf,y}= {1'b0, a & b};
            3'b011: {cf,y}= {1'b0, a | b};
            3'b100: {cf,y}= {1'b0, a ^ b};
            default: begin
                    cf = 0;
                    y = 0;
             end
        endcase

    end










endmodule

 

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