module alu4(
input [3:0]a,b,
input [2:0]op,
output reg [3:0]y,
output reg cf
);
reg carry,borrow;
always@(*)begin
y=4'b0;
cf=1'b0;
case(op)
3'b000 :
begin
{carry,y} = a + b;
cf=carry;
end
3'b001 :
begin
{borrow,y} = (a + ~b + 1);
cf=borrow;
end
3'b010 : y = a & b;
3'b011 : y = a | b;
3'b100 : y = a ^ b;
default: y = 4'b0000;
endcase
end
endmodule