71. Arithmetic Logic Unit

How do you plan to solve it?

/*Write your code here*/
module alu4(
    input [3:0] a,b,
    input [2:0] op,
    output reg [3:0] y,
    output reg cf
);
    reg [4:0] y_ext;

    always @* begin
        case (op) 
            3'b000: begin
                y_ext = {1'b0, a} + {1'b0, b};
                y = y_ext[3:0];
                cf = y_ext[4];
            end
            3'b001: begin
                y_ext = {1'b0, a} + {1'b0, ~b} + 5'b1;
                y = y_ext[3:0];
                cf = ~y_ext[4];
            end
            3'b010: begin
                y = a & b;
                cf = 1'b0;
            end
            3'b011: begin
                y = a | b;
                cf = 1'b0;
            end
            3'b100: begin
                y = a ^ b;
                cf = 1'b0;
            end
            default: begin
                y = 4'b0;
                cf = 1'b0;
            end
        endcase
    end
endmodule