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71. Arithmetic Logic Unit

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Solving Approach

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Code

module alu4(
    input [3:0] a, b,
    input [2:0] op,
    output reg [3:0]  y,
    output reg cf
);

parameter ADD = 3'b000;
parameter SUB = 3'b001;
parameter AND = 3'b010;
parameter OR  = 3'b011;
parameter XOR = 3'b100;

always @(*) begin
    case (op)

    ADD: {cf,y} = a + b;
    SUB: {cf,y} = a + ~b + 1'b1;
    AND: {cf,y} = {1'b0,a & b};
    OR: {cf,y} = {1'b0, a|b};
    XOR: {cf,y} = {1'b0,a^b};

    default: {cf,y} = 5'b00000;


    endcase

end

endmodule

 

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