71. Arithmetic Logic Unit

How do you plan to solve it?

module alu4 (
    input  [3:0] a,
    input  [3:0] b,
    input  [2:0] op,
    output reg [3:0] y,
    output reg cf
);

    reg [4:0] temp;  

    always @(*) begin
        case (op)
            3'b000: begin // ADD
                temp = a + b;
                y  = temp[3:0];
                cf = temp[4];  // carry
            end

            3'b001: begin // SUB (a - b = a + ~b + 1)
                temp = a + (~b) + 1;
                y  = temp[3:0];
                cf = (a<b);  // borrow = NOT carry_out
            end

            3'b010: begin // AND
                y  = a & b;
                cf = 1'b0;
            end

            3'b011: begin // OR
                y  = a | b;
                cf = 1'b0;
            end

            3'b100: begin // XOR
                y  = a ^ b;
                cf = 1'b0;
            end

            default: begin // Reserved
                y  = 4'b0000;
                cf = 1'b0;
            end
        endcase
    end

endmodule