71. Arithmetic Logic Unit

How do you plan to solve it?

module alu4 (
    input  wire [3:0] a,
    input  wire [3:0] b,
    input  wire [2:0] op,
    output reg  [3:0] y,
    output reg        cf
);

reg [4:0] temp;

always @(*) begin
    y  = 4'b0000;
    cf = 1'b0;

    case (op)

        // ADD
        3'b000: begin
            temp = {1'b0, a} + {1'b0, b};
            y    = temp[3:0];
            cf   = temp[4];
        end

        // SUB
        3'b001: begin
            temp = {1'b0, a} + {1'b0, ~b} + 5'b00001;
            y    = temp[3:0];
            cf   = ~temp[4];
        end

        // AND
        3'b010: begin
            y = a & b;
            cf = 1'b0;
        end

        // OR
        3'b011: begin
            y = a | b;
            cf = 1'b0;
        end

        // XOR
        3'b100: begin
            y = a ^ b;
            cf = 1'b0;
        end

        default: begin
            y  = 4'b0000;
            cf = 1'b0;
        end
    endcase
end

endmodule