71. Arithmetic Logic Unit

How do you plan to solve it?

module alu4(
    input [3:0]a,
    input [3:0] b,
    input [2:0] op,
    output reg [3:0] y,
    output reg cf
);
wire[4:0] add5 = {1'b0, a} + {1'b0, b};
wire[4:0] sub5 = {1'b0,a} + {1'b0, ~b} + 5'b1;
always @(*) begin
    y = 4'b0000;
    cf = 1'b0;
    case(op) 
    3'b000 : begin
        y = add5[3:0];
        cf = add5[4];
    end
    3'b001 : begin
        y = sub5[3:0];
        cf = ~sub5[4];
    end
    3'b010 : y = a & b;
    3'b011 : y = a | b;
    3'b100 : y = a ^ b;
    default : begin y = 4'b0000; cf = 1'b0; end
    endcase
end

endmodule