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71. Arithmetic Logic Unit

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Solving Approach

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Code

/*Write your code here*/
module alu4
(
input wire [3:0] a,b,
input wire [2:0] op,
output reg [3:0] y,
output reg cf
);
reg carry;
always@*
begin
    case(op)
    3'd0:begin
            {carry,y}=a+b;
            cf=carry;
        end
    3'd1:begin
            y=a-b;
            cf= a < b ? 1 : 0;
        end
    3'd2:begin
            y=a&b;
            cf=0;
        end
    3'd3:begin
            y=a|b;
            cf=0;
        end
    3'd4:begin
            y=a^b;
            cf=0;
        end
    default:begin
                y=4'd0;
                cf=0;
            end
    endcase
end

endmodule

 

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