How do you plan to solve it?
/*Write your code here*/
module alu4 (a,b,op,y,cf);
input [3:0] a,b;
input [2:0] op;
output reg [3:0] y;
output reg cf;
reg carry;
always @(*) begin
y = 4'b0000;
cf = 1'b0;
carry = 1'b0;
case (op)
3'b000: begin // ADD
{carry, y} = {1'b0, a} + {1'b0, b};
cf = carry;
end
3'b001: begin // SUB
{carry, y} = {1'b0, a} + {1'b0, ~b} + 1'b1;
cf = ~carry; // borrow
end
3'b010: begin // AND
y = a & b;
cf = 1'b0;
end
3'b011: begin // OR
y = a | b;
cf = 1'b0;
end
3'b100: begin // XOR
y = a ^ b;
cf = 1'b0;
end
default: begin
y = 4'b0000;
cf = 1'b0;
end
endcase
end
endmodule