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71. Arithmetic Logic Unit

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Solving Approach

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Code

module alu4(
    input [3:0] a,
    input [3:0] b,
    input [2:0] op,
    output reg [3:0] y,
    output reg cf
);
    localparam [2:0]
        OP_ADD = 3'b000,
        OP_SUB = 3'b001,
        OP_AND = 3'b010,
        OP_OR  = 3'b011,
        OP_XOR = 3'b100;

    reg [4:0] sum5;

    always @* begin
        y = 4'b0000;
        cf = 1'b0;

        case (op)
            OP_ADD: begin
                sum5 = { 1'b0, a } + { 1'b0, b };
                y = sum5[3:0];
                cf = sum5[4];
            end

            OP_SUB: begin
                sum5 = { 1'b0, a } + { 1'b0, ~b } + 5'b00001;
                y = sum5[3:0];
                cf = ~sum5[4];
            end

            OP_AND: y = a & b;
            OP_OR: y = a | b;
            OP_XOR: y = a ^ b;
        endcase
    end
endmodule

 

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