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71. Arithmetic Logic Unit

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Code

module alu4(
    input [3:0] a, b,
    input [2:0] op,
    output reg [3:0] y,
    output reg cf
); 
    always @(*) begin 
        cf = 0;
        case(op)
            3'b000: {cf,y} = a + b;
            3'b001: {cf,y} = a + ~b + 1;
            3'b010: y = a & b;
            3'b011: y = a | b;
            3'b100: y = a ^ b;
            default: y = 0; 
        endcase
    end
endmodule

 

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