82. Asynchronous MOD-5 Down Counter

Solution Explanation

Set all T inputs HIGH. For positive-edge-triggered T flip-flops, connect each Q output to the next stage's clock input so the count ripples downward:

T0 = T1 = T2 = 1
CLK0 = Clock
CLK1 = Q0
CLK2 = Q1

Q0 toggles on every rising edge of the external Clock. A rising transition at Q0 toggles Q1, and a rising transition at Q1 toggles Q2.

After ripple propagation settles, the counter follows 110, 101, 100, 011, and 010.

A three-input NAND gate detects the temporary state 001 using Q2’, Q1’, and Q0. Its active-low rollover output is:

~ROLL = (Q2’ · Q1’ · Q0)’
Signal = ~Reset · ~ROLL
       = ~Reset · (Q2’ · Q1’ · Q0)’

Connect Signal to the active-low PRE inputs of the Q2 and Q1 flip-flops and to the active-low CLR input of the Q0 flip-flop. Hold the other asynchronous PRE and CLR inputs HIGH.

When the counter briefly reaches 001, ~ROLL becomes LOW, making Signal LOW. PRE sets Q2 and Q1 to 1, while CLR resets Q0 to 0, forcing 110.

When ~Reset = 0, Signal also becomes LOW and initializes the same 110 state regardless of the Clock.