45. BCD to Excess-3 Converter

• Output Select Analysis: By treating the invalid decimal combinations (1010 through 1111) as don't-care states, Karnaugh maps simplify the logic equations to add three to the incoming data efficiently. The lowest bit E0 simply requires inverting the lowest input bit.
• Hardware Optimization: The circuit splits the BCD inputs into inverted and non-inverted signal paths using NOT gates. These lines feed into separate AND-OR networks for E3, E2, and E1, minimizing the transistor footprint while ensuring precise code translation.

Boolean Equations:

• E3 = D3 + (D2 . D1) + (D2 . D0)
• E2 = (D2 . ~D1 . ~D0) + (~D2 . D1) + (~D2 . D0)
• E1 = (~D1 . ~D0) + (D1 . D0)
• E0 = ~D0