A. Dataflow
module sub4_2c (
input [3:0] a,
input [3:0] b,
output [3:0] diff,
output bout
);
// Width-safe 5-bit add to capture carry-out
wire [4:0] sum5 = {1'b0, a} + {1'b0, ~b} + 5'b00001;
assign diff = sum5[3:0];
assign bout = ~sum5[4]; // borrow = NOT carry-out
endmodule
B. Structural via ripple adder
module full_adder_1bit(
input a, b, cin,
output sum, cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
module rca4_add (
input [3:0] x, y,
input cin,
output [3:0] sum,
output cout
);
wire c1, c2, c3;
full_adder_1bit fa0(.a(x[0]), .b(y[0]), .cin(cin), .sum(sum[0]), .cout(c1));
full_adder_1bit fa1(.a(x[1]), .b(y[1]), .cin(c1 ), .sum(sum[1]), .cout(c2));
full_adder_1bit fa2(.a(x[2]), .b(y[2]), .cin(c2 ), .sum(sum[2]), .cout(c3));
full_adder_1bit fa3(.a(x[3]), .b(y[3]), .cin(c3 ), .sum(sum[3]), .cout(cout));
endmodule
module sub4_2c (
input [3:0] a,
input [3:0] b,
output [3:0] diff,
output bout
);
wire [3:0] b_inv = ~b;
wire cout;
rca4_add adder(.x(a), .y(b_inv), .cin(1'b1), .sum(diff), .cout(cout));
assign bout = ~cout;
endmodule
