49. Brake Light Control

module brake_light (
    input  brake_pedal,
    output reg brake_light
);
    always @(*) begin
        if (brake_pedal)
            brake_light = 1;
        // Comment else block to see latching behavior
        else
            brake_light = 0; // explicitly handle else → no latch
    end
endmodule

💡Remember

• Combinational circuits cannot remember state.
• If some input conditions don’t assign an output, Verilog infers a latch to “remember”.
• Always cover all conditions: add else or use a default assignment.