Testbench Code
`timescale 1ns/1ps
module tb_brake_light;
// Input
reg brake_pedal;
// DUT output
wire brake_light;
// Expected (prefixed expected_)
wire expected_brake_light;
// Mismatch signal
reg mismatch;
wire mismatch_w = (brake_light !== expected_brake_light);
// Counters
integer TOTAL_TEST_CASES = 0;
integer TOTAL_PASSED_TEST_CASES = 0;
integer TOTAL_FAILED_TEST_CASES = 0;
// VCD control
integer VCD_MAX_CASES = 32;
// DUT
brake_light dut(.brake_pedal(brake_pedal), .brake_light(brake_light));
// Golden model (no latch, pure comb)
assign expected_brake_light = (brake_pedal) ? 1'b1 : 1'b0;
// VCD dump (ordered: Inputs → Outputs → Expected → Mismatch)
initial begin
$dumpfile("tb_brake_light.vcd");
$dumpvars(0,
tb_brake_light.brake_pedal, // Input
tb_brake_light.brake_light, // DUT output
tb_brake_light.expected_brake_light,// Expected
tb_brake_light.mismatch // Mismatch
);
$dumpon; // start at time 0
end
// Init and header
initial begin
brake_pedal = 1'b0;
mismatch = 1'b0;
$display("brake_pedal | DUT_brake_light | expected_brake_light | mismatch");
$display("---------------------------------------------------------------");
end
// Apply + check task
task apply_and_check;
input t_pedal;
begin
brake_pedal = t_pedal;
#1; // settle
mismatch = mismatch_w;
TOTAL_TEST_CASES++;
if (!mismatch) TOTAL_PASSED_TEST_CASES++;
else TOTAL_FAILED_TEST_CASES++;
$display(" %b | %b | %b | %0d",
brake_pedal, brake_light, expected_brake_light, mismatch);
if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
end
endtask
// Stimulus (full truth table)
initial begin
apply_and_check(1'b0);
apply_and_check(1'b1);
// Summary
$display("---------------------------------------------------------------");
$display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
$display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
$display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
$display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true":"false");
#2 $finish;
end
endmodule