77. Design 4-bit Asynchronous Down Counter

Asynchronous Down Counter: A 4-bit asynchronous down counter decreases its count from 1111 (15) to 0000 (0) using four T Flip-Flops. The T inputs are kept HIGH (1) so each flip-flop toggles whenever it receives a clock transition.

Ripple Clocking: The external CLK is connected to the first flip-flop, while the Q output of each flip-flop drives the clock input of the next stage. This creates a ripple effect, where each stage toggles based on the previous stage output.

Reset Initialization: The active-low ~RESET input is connected to the PRE inputs of all flip-flops. When ~RESET = 0, all flip-flops are asynchronously preset to 1111 (F), setting the initial count value.

Counting Operation: After reset is released, each incoming clock pulse toggles the flip-flops through ripple propagation, producing the down-counting sequence:

1111 → 1110 → 1101 → ... → 0001 → 0000 → 1111 → ...

Thus, the counter continuously performs a modulo-16 asynchronous down count.