60. Implement JK Latch with EN, PRE, CLR

SR Flip-Flop Limitation: In a gated SR Flip-Flop, asserting S = 1 and R = 1 simultaneously while enabled forces both outputs to the same logic level, violating the complementary condition (Q_n ≠ ~Q_n). When the enable signal goes low, the circuit may enter a race condition, making the final state unpredictable.

How the JK Flip-Flop Solves It: The JK Flip-Flop feeds Q_n back to the K input and ~Q_n back to the J input.

If Q_n = 1, the J path is disabled and the K path is enabled.

If Q_n = 0, the J path is enabled and the K path is disabled.

Thus, when J = 1 and K = 1, only one input is effective based on the current state, causing the flip-flop to toggle on each active clock edge instead of entering an invalid state (Q_n+1 = ~Q_n).

Asynchronous override: The PRE and CLR inputs operate independently of the EN signal. Because they are cross-coupled directly into the output NAND gates, they immediately override any synchronous commands.