59. Implement SR Latch with EN, PRE, CLR

Circuit Architecture: The design extends a gated SR latch by replacing the NOT gate with NAND gate with one common input Enable and a cross-coupled 2-input NAND gates with 3-input NAND gates. The third input enables active-low asynchronous Preset (PRE) and Clear (CLR) while retaining synchronous Set, Reset control.

Asynchronous Override (Active-Low):

• PRE = 0, CLR = 1: Forces Q_n = 1 and ~Q_n = 0, regardless of S, R, or EN.
• PRE = 1, CLR = 0: Forces Q_n = 0 and ~Q_n = 1, regardless of S, R, or EN.
• PRE = 0, CLR = 0: Both outputs become 1, creating the forbidden state.

Synchronous Operation (PRE = 1, CLR = 1):

• The circuit behaves as a standard gated SR latch.
• EN = 0: Holds the previous state (Q_n, ~Q_n).
• EN = 1: Samples the inputs:
  • S = 1, R = 0: Sets Q_n = 1.
  • S = 0, R = 1: Resets Q_n = 0.