58. Maximum of Two Numbers

module max2_func (
    input  [7:0] a,
    input  [7:0] b,
    output [7:0] max
);
    function [7:0] max2;
        input [7:0] x, y;
        begin
            max2 = (x > y) ? x : y;
        end
    endfunction

    assign max = max2(a, b);
endmodule

💡Remember

A Verilog function returns one value and must be timing-free (no #, @, wait).
You can call functions in continuous assignments or inside always @*.
Keep combinational outputs fully driven to avoid latches.