Testbench Code

`timescale 1ns/1ps

module tb_max2_func;
    // 1) Inputs
    reg  [7:0] a, b;

    // 2) DUT output
    wire [7:0] max;

    // 3) Expected (prefixed expected_)
    reg  [7:0] expected_max;

    // 4) Mismatch (HIGH if outputs do not match expected)
    reg  mismatch;
    wire mismatch_w = (max !== expected_max);

    // Logging
    integer TOTAL_TEST_CASES=0, TOTAL_PASSED_TEST_CASES=0, TOTAL_FAILED_TEST_CASES=0;
    integer VCD_MAX_CASES = 32;

    // Seed
    integer seed;
    initial seed = 32'hA5A5_1357 ^ $time;

    // DUT
    max2_func dut(.a(a), .b(b), .max(max));

    // VCD (Inputs → Outputs → Expected → Mismatch)
    initial begin
        $dumpfile("tb_max2_func.vcd");
        $dumpvars(0,
            tb_max2_func.a, tb_max2_func.b,       // Inputs
            tb_max2_func.max,                     // Output
            tb_max2_func.expected_max,            // Expected
            tb_max2_func.mismatch                 // Mismatch
        );
        $dumpon;
    end

    // Header
    initial begin
        a=0; b=0; mismatch=0; expected_max=0;
        $display("   a     b   |  max  | expected_max | mismatch");
        $display("------------------------------------------------");
    end

    // Apply + check (compute expected BEFORE wait)
    task apply_and_check;
        input [7:0] ta, tb;
        begin
            a = ta; b = tb;

            expected_max = (ta > tb) ? ta : tb; // expected first
            #1;                                 // let DUT settle
            mismatch = mismatch_w;

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch) TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            else           TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;

            $display("0x%02h 0x%02h | 0x%02h |    0x%02h     |    %0d",
                     a, b, max, expected_max, mismatch);

            if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
        end
    endtask

    integer i;
    reg [7:0] ta, tb;  // temps avoid expression part-selects

    initial begin
        // Directed
        apply_and_check(8'h00, 8'h00);
        apply_and_check(8'h01, 8'h02);
        apply_and_check(8'h10, 8'h0F);
        apply_and_check(8'h7F, 8'h80);
        apply_and_check(8'hFF, 8'h00);
        apply_and_check(8'h3C, 8'hC3);
        apply_and_check(8'h55, 8'hAA);
        apply_and_check(8'hAA, 8'h55);

        // Small sweep (use temps + masking to 8 bits)
        for (i = 0; i < 8; i = i + 1) begin
            ta = i[7:0];
            tb = (8'hF0 + i) & 8'hFF;   // mask to 8 bits instead of (expr)[7:0]
            apply_and_check(ta, tb);
        end

        // Randomized (truncate to 8 bits via vector assignment)
        repeat (8) begin
            ta = $random(seed);
            tb = $random(seed);
            apply_and_check(ta, tb);
        end

        // Summary
        $display("------------------------------------------------");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        #2 $finish;
    end
endmodule