87. Multi-Scale System Clock Frequency Divider Circuit

In an asynchronous counter, flip-flops do not share one clock.

• T_FF_0 receives the external Clock.
• Each remaining flip-flop receives its clock from the output of the previous flip-flop.
• T is fixed at 1, so every active clock edge toggles the stage.

Asynchronous Up Counter

• Circuit uses positive edge triggered flip flops.
• T_FF_0 toggles from the external clock.
• Each higher stage toggles after the previous output changes from 0 to 1.
• Q' output is used to clock the next stage.

000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000

Asynchronous Down Counter

A 3-bit down counter decreases its state by one. With rising-edge flip-flops, Q clocks the next stage.

• Circuit uses positive edge triggered flip flops.
• T_FF_0 toggles from the external clock.
• Each higher stage toggles after the previous output changes from 0 to 1.
• Q of each stage drives the next clock.

111 → 110 → 101 → 100 → 011 → 010 → 001 → 000 → 111

Asynchronous Counter Direction:

Counting direction depends on the flip-flop edge, the output used as the next clock, and the pins used as counter outputs.

Out_A: 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000
Out_B: 111 → 110 → 101 → 100 → 011 → 010 → 001 → 000 → 111

Controlled Asynchronous Up-Down Counter

The control signal C selects the clock source of every higher flip-flop.

C = 0: 111 → 110 → 101 → 100 → 011 → 010 → 001 → 000 → 111
C = 1: 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000

Note: Change C only when counting is disabled and the outputs are stable. Changing it during operation can switch the selected ripple-clock path and create an unwanted clock edge.

A MOD-x counter uses exactly x valid states before repeating.

• PRESET and CLEAR inputs redirect an unwanted state to the required valid state.
• The decoding gate must briefly detect the first unwanted state.

MOD-6 Up counter

A MOD-6 up counter uses states 000 to 101. State 110 is detected and cleared.

NAND output = (Q₂ · Q₁ · Q₀')'
000 → 001 → 010 → 011 → 100 → 101 → 000

Invalid state recovery

• NAND detection: When 110 appears, Q₂ = 1, Q₁ = 1, and Q₀ = 0. The NAND output becomes LOW.
• Valid-state return: The active-LOW clear inputs immediately force 000.

A T flip-flop with T = 1 divides its clock frequency by two. Cascaded stages divide it repeatedly.

• Clock = 16 kHz enters the first stage.
• Q₀', Q₁', Q₂', and Q₃' give 8, 4, 2, and 1 kHz respectively.
• A normal and inverted output have the same frequency.

fQₖ = fCLK / 2^(k+1), where Q₀ is the first stage

Counter outputs do not change together because every stage waits for the previous stage.

Delay to Qₖ ≈ (k + 1) · tpd
Maximum settling delay for N stages ≈ N · tpd

Where,
k   = flip flop stage index, starting from 0
N   = total number of counter stages
tpd = propagation delay of one flip-flop
(assuming all flip-flops have the same propagation delay)

Effects

• Temporary intermediate counts can appear during a transition.
• Decoded outputs may produce short glitches.
• The maximum safe clock frequency becomes lower.

In a synchronous counter, every flip-flop shares the same clock. All state bits update together at the active edge.

Synchronous Up Counter

000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000

T₀ = 1
T₁ = Q₀
T₂ = Q₁ · Q₀

A flip-flop toggles when all its lower-order bits are HIGH.

Synchronous Down Counter

111 → 110 → 101 → 100 → 011 → 010 → 001 → 000 → 111

T₀ = 1
T₁ = Q₀'
T₂ = Q₁' · Q₀'

A flip-flop toggles when all its lower-order bits are LOW.

Synchronous Up-Down Counter

• C = 0 selects down counting.
• C = 1 selects up counting.

T₀ = 1
T₁ = Q₀ ⊙ C
T₂ = (Q₀ ⊙ C) · (Q₁ ⊙ C)

A synchronous MOD counter assigns the required next valid state through combinational logic at the flip-flop inputs.

Invalid State Operations

Don't Care method

Invalid-state next values are marked X during logic minimization.

• Advantages:
• Usually produces simpler input equations.
• Uses fewer gates.
• Limitations:
• Recovery from an invalid state is not guaranteed.
• The counter may enter an unintended loop.

X = either HIGH or LOW; the value is chosen only to simplify the logic.

Self-Recovery Method:

Every invalid state is assigned a known valid next state.

• Advantage:
• The counter automatically returns to its valid sequence.
• Startup and fault behavior are predictable.
• Limitation:
• The equations may require more gates.
• Every invalid state must be defined and verified.

MOD-11 Down Counter (counts from 10 to 0)

1010 → 1001 → 1000 → 0111 → 0110 → 0101 → 0100 → 0011 → 0010 → 0001 → 0000 → 1010

This example uses self-recovery: every invalid state from 1011 to 1111 returns to 1010.

When ~Reset = 0, the counter asynchronously resets to 1010 and holds this state while Reset remains LOW.

T₃ = Q₂' · Q₁' · Q₀'
T₂ = (Q₂ + Q₃) · Q₁' · Q₀' + Q₃ · Q₂
T₁ = Q₃ · Q₂ · Q₁' + (Q₃' + Q₂') · Q₀'
T₀ = Q₀ + Q₂' · Q₁ + (Q₂ ⊕ Q₃)

A synchronous binary up counter can be used directly as a frequency divider.

T₀ = 1
T₁ = Q₀
T₂ = Q₁ · Q₀
T₃ = Q₂ · Q₁ · Q₀
T₄ = Q₃ · Q₂ · Q₁ · Q₀
T₅ = Q₄ · Q₃ · Q₂ · Q₁ · Q₀

All flip-flops update together, but the next clock edge must wait for the flip-flop and input logic delays.

TCLK(min) ≥ tCQ(max) + tlogic(max) + tsetup

where:
TCLK(min)  = minimum allowable clock period
tCQ(max)   = maximum clock-to-Q delay of a flip-flop
tlogic(max)= maximum propagation delay through the combinational logic
tsetup     = setup-time requirement of the receiving flip-flop

Therefore, fCLK(max) ≤ 1 / TCLK(min).

A custom sequence generator is a counter that follows a user-defined state order.

000 → 110 → 010 → 101 → 111 → 100 → 011 → 001 → 000

Define the required next state for each current state, then use the T flip-flop excitation relation to determine each T input.

When ~Reset = 0, the counter will asynchronously reset to 000 and holds the value

T₂ = Q₀'
T₁ = (Q₂ ⊙ Q₀) + (Q₂ ⊕ Q₁)
T₀ = Q₂ ⊕ Q₁ ⊕ Q₀

A 3-bit counter stores the number of available parking slots from 0 to 7.

Sensor edge detection

Active-LOW sensors ENT and EXT use falling-edge detectors. Each detector stores the current and previous samples.

ENT_P = (ENT_NOW' · ENT_PREV)'
EXT_P = (EXT_NOW' · EXT_PREV)'

• ENT_P = 0 for one event when a vehicle enters.
• EXT_P = 0 for one event when a vehicle exits.
• At all other times, both pulse outputs remain HIGH.

Boundary Logic

The output bits Q₂, Q₁, and Q₀ detect the two count limits.

FULL = Q₂' · Q₁' · Q₀'
EMPTY = Q₂ · Q₁ · Q₀

• FULL = 1 at 000: no slot is available.
• EMPTY = 1 at 111: all seven slots are available.

Reset Logic

When ~Reset = 0, the counter asynchronously resets to 000 and holds this state while Reset remains LOW.

Valid Direction Logic (UPV and DNV)

A single valid sensor pulse creates one active-HIGH direction request. Boundary flags block overflow and underflow.

UPV = EXT_P' · ENT_P · EMPTY'
DNV = ENT_P' · EXT_P · FULL'

• UPV = 1: An exit pulse increments the available-slot count when EMPTY = 0.
• DNV = 1: An entry pulse decrements the count when FULL = 0.

Counter Enable and T input Logic:

COUNTEN becomes HIGH only for one valid increment or decrement request.

COUNTEN = UPV + DNV
T₀ = COUNTEN
T₁ = COUNTEN · (Q₀ ⊙ UPV)
T₂ = COUNTEN · (Q₀ ⊙ UPV) · (Q₁ ⊙ UPV) = T₁ · (Q₁ ⊙ UPV)

If COUNTEN = 0, every T input is LOW and the count holds.

Parking LED Flag Logic

The active-HIGH LEDs show whether at least one slot is available.

GREEN = FULL'
RED = GREEN' = FULL

• RED = 1 only when the count is 000.
• GREEN = 1 for counts 001 to 111.