29. One Shot Pulse

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    // Synchronous reset + edge detect
    // pulse = (~prev & sig_in) when not in reset; else 0
    pulse <= rst ? 1'b0 : ((~prev) & sig_in);
    // prev samples current input (or clears on reset)
    prev  <= rst ? 1'b0 : sig_in;
  end
endmodule