29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,
  input  wire sig_in,
  output reg  pulse
);

  reg prev;  // previous value of sig_in

  always @(posedge clk) begin
    if (rst) begin
      prev  <= 1'b0;
      pulse <= 1'b0;
    end else begin
      // Pulse only when sig_in transitions 0 -> 1
      pulse <= (~prev) & sig_in;

      // Update history for next cycle
      prev <= sig_in;
    end
  end

endmodule