29. One Shot Pulse

on rst, we reset both pulse and history of sig_in, which is prev, to 0. In case rst isnt high, we assign the AND of current sig_in and NOT of prev, to ensure that it detects only the rising edge of sig_in which is the only case in which prev will be low as previous case of sig_in was low. We also constantly update prev to match the current value of sig_in according to the posedge of clock. 

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    // Write your code here
    if (rst) begin
      pulse <= 0;
      prev <= 0;
    end else begin
      pulse <= sig_in & ~prev;
      prev <= sig_in;
    end
  end
endmodule