29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
     if(rst) begin
       pulse <= 1'b0;
       prev <= 1'b0;
     end
     else begin
      pulse <= sig_in && !(prev);
      prev <= sig_in;
     end
  end
endmodule