29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    if (rst) begin
      pulse <= 1'b0;
      prev  <= 1'b0;
    end
    else if ((sig_in == 1) & (prev == 0)) begin
      pulse <= 1'b1;
      prev  <= 1'b1;
    end
    else if ((sig_in == 1'b0)) begin
      prev  <= 1'b0;
      pulse <= 1'b0;
    end
    else begin
      pulse <= 1'b0;
    end
  end
endmodule