29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
    input  wire clk,
    input  wire rst,
    input  wire sig_in,
    output reg  pulse
);

    reg sig_d;  // previous-cycle sampled value

    always @(posedge clk) begin
        if (rst) begin
            sig_d <= 1'b0;
            pulse <= 1'b0;
        end else begin
            pulse <= (~sig_d) & sig_in;  // 1 only on 0→1 transition
            sig_d <= sig_in;             // update history
        end
    end

endmodule