29. One Shot Pulse

How do you plan to solve it?

• Store the previous clocked value of sig_in in a register.
• On each rising clock edge, generate a pulse only when prev=0 and sig_in=1.
• Use concatenation to update both prev and pulse in one line.
• Synchronous reset clears both registers to 0.

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    if (rst)
        {prev, pulse} <= 2'b00;
    else
        {prev, pulse} <= {sig_in, (~prev & sig_in)};
  end
endmodule