29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    // Write your code here
    if(rst) begin
    pulse<=1'b0;
   prev<=1'b0;
    end
    else begin
     
      if(~prev && sig_in) begin pulse<=1'b1; end 
      else pulse<=1'b0;
        prev<=sig_in;
    end
   
  end
endmodule