29. One Shot Pulse

How do you plan to solve it?

// module rise_pulse(
//   input  wire clk,
//   input  wire rst,      // synchronous active-high reset
//   input  wire sig_in,
//   output reg  pulse
// );
//   reg prev;             // previous sampled value of sig_in

//   always @(posedge clk) begin
//     // Write your code here
//     pulse <= 1'b0;
//     if(rst) begin
//       prev <= 1'b0;
//       pulse <= 1'b0;
//     end
//     else if(~prev & sig_in) begin
//       pulse <= 1'b1;
      
//     end
//     prev <= sig_in;
//   end

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
      if(rst) begin
        prev  <= 1'b0;
        pulse <= 1'b0;
      end
      else begin
        // This logic says: "If it was 0 and now it's 1, pulse is 1. Otherwise, 0."
        pulse <= (~prev & sig_in); 
        prev  <= sig_in;
      end
  end
endmodule