29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev=1'b0;             // previous sampled value of sig_in

  always @(posedge clk) begin
    // Write your code here
    if(rst) begin
      pulse<=1'b0;
      prev<=1'b0;
    end
    if(sig_in) begin
      if(prev==1'b1)begin
        pulse<=0;
      end
      else begin
        pulse<=1;
        prev<=1'b1;
      end
    end
    else begin
      prev<=1'b0;
      pulse<=0;
    end
  end
endmodule